FAQ about SRAM PUFs
Q: Can SRAM that is used for a PUF be reused by other application afterwards?
A: It is typically recommended to use dedicated SRAM as a PUF and hence do not allow reuse by other applications. However, it may be possible to allow reuse in custom cases depending on the application. The following requirements should be met:
- PUF functionality is only used during boot of the device, it is not needed afterwards.
- RESET does not give a problem for the application: RESET typically makes the chip boot again, however it does not necessarily mean that the SRAM is also repowered! If RESET does not trigger repower of the SRAM and SRAM was overwritten by other application, a PUF cannot recover the key anymore.
- Ageing of SRAM needs to be investigated, since typical anti-ageing methods will not work.
Q: Does SRAM reading have to be done within some period of time after power on? Will the PUF key be the same after we power the device and keep it on for long period of time?
A: Technically PUF algorithms do not need to be run directly after power up. Once the SRAM is powered up, the startup values stay the same. However, leaving the SRAM in this state for prolonged time can have a negative effect on the aging of the device. This is why we recommend running our algorithms early on, to allow the algorithms to counter aging effects. This means that after the PUf algorithms has run there will be an anti-aging pattern left in the SRAM PUF area and not the original startup pattern.
Q: 4.4. What are the power requirements for SRAM to be used as PUF?
A: To get good SRAM start-up behavior it is recommended that the voltage power-up curve of the SRAM power supply meets the following guidelines:
- Power supply voltage must be monotonically increasing (no power dips during voltage ramp-up).
- Power supply voltage rise time from 0V to 90% of Vdd must be less than 0.5ms.
- Before power-on, the power supply must have been at 0V for a sufficiently long time in order to guarantee fresh startup values in the SRAM memory. Typically a power-off time of 100ms is enough. For extreme low temperatures (-40C and below) the required power-off time may need to be extended to around 500ms.
Can you please brief about the power requirements? Will it be in terms of ms? If the same design is done using cadence should we power-up in terms of ms? I am a beginner, please clear me.
@hema: Thanks for your questions. When powering up an SRAM the rise time should not be too slow, as this can have negative impact on the PUF behavior. That is why we recommend the power-up time to be faster than 0.5ms. There is no hard minimum rise-time requirement.
How to confirm that the responses obtained from a PUF circuit are only due to manufacturing variations? Is the predictions can be done purely based on randomness?
@hema: I am not sure I fully understand your question, but let me try to answer it as best as I can.
Typically the quality of a PUF circuit is determined by performing many measurements and verifying that it behaves as one expects. This means that between different responses from the same PUF there is some noise, but this noise should be within the bounds of error-correcting codes. Also, measurements from different PUFs should be significantly different. Based on measuring these two aspects, one can determine how strong the error-correction should be to always retrieve the same fingerprint from the same PUF and how many PUF response bits are required to get enough entropy from the PUF to be able to uniquely distinguish different PUF instances.
I hope this answers your question.